Space and military systems used in strategic applications are often built using radiation hardened microelectronics. Radiation hardened microelectronics are ruggedized to withstand the deleterious effects of ionizing radiation exposure. Radiation hardened technologies use a combination of design and process techniques and potentially new materials to harden microelectronics. Complementary Metal Oxide Semiconductor (CMOS) integrated circuits (ICs) have been and continue to be the largest category of microelectronics. Radiation hardened CMOS microelectronics are essential in space and military system applications where the certainty of radiation exposure must not be allowed to threaten the mission.
The natural and man-made radiation spectrum includes highly-energetic charged particles accelerating along uncorrelated trajectories from a variety of sources as well as high-energy mega-bursts of particles and photons. When energetic charged particles or photons interact with microelectronics some of their energy is absorbed by the electronics creating electron-hole pairs (free excess charge) within the constituent semiconductor materials of the electronics. This radiation-induced excess charge when collected within sensitive regions of microcircuits can destroy stored information and in extreme events can permanently damage the electronics (e.g., burnout). Specific design and process hardening techniques are commonly used to mitigate the effects of radiation on microelectronics to prevent logic upsets, but these techniques are becoming increasing less effective in scaled technologies. New hardening approaches are required. This present invention presents a new approach that if necessary can be easily used in concert with the currently practiced techniques to more effectively harden digital CMOS technologies against single-event charged particle-induced logic upsets and prompt-dose (i.e., high ionizing dose rate) induced logic upsets.
Full static CMOS logic design involves the pairing of N-channel Field Effect Transistors (NFETs) with complementary P-channel Field Effect Transistors (PFETs). CMOS logic is characterized by its low quiescent power dissipation. Steady state CMOS digital logic gates invariably involve one transistor type being “ON” while the complementary transistor type is “OFF,” so there is never a sustained direct current path coupling the power rails (i.e., VDD and GND). The simple schematic for a CMOS inverter circuit is shown in FIG. 1.
The NFET and PFET of the CMOS inverter share a common gate (G) node, gated by input voltage VIN, and their drain (D) nodes are connected together to provide the output voltage VOUT. The NFET source (S) and substrate (Sx) nodes are connected to ground (GND) while the PFET source (S) and substrate (Sx) nodes are connected to the supply voltage (VDD). When VIN is HIGH (i.e., VIN=VDD) the NFET is “ON” and the PFET is “OFF” and thus VOUT is LOW (i.e., VOUT=GND). When VIN is LOW (i.e., VIN=GND) the NFET is “OFF” and the PFET is “ON” and thus VOUT is HIGH (i.e., VOUT=VDD).
A simplified physical cross-section of a CMOS inverter is shown in FIG. 2. (Though lacking some of the physical detail of CMOS technology (e.g., shallow trench isolation, drain/source region diffusion extensions, multi-level metal interconnects), this simple cross-section is adequate for the discussions that follow).
The cross-section of an N-well, P-epitaxial/bulk CMOS technology is illustrated here and will be used to describe the features of this buried power grids though the concepts to be described herein can be applied equally to any CMOS construction. The NFET is built into the p epi overlying the starting p+ substrate and a shallow, retrograde n-well is formed within the p epi to accommodate the PFET. Metal connections are used to configure the inverter circuit. (The full interconnect detail cannot be shown in this simple two-dimensional illustration).
In the event that a highly-energetic charged particle (i.e., ion) strikes a microcircuit, excess electron-hole pairs are generated in a dense plasma along the track of the particle through the semiconductor. If the ion strike occurs on or near a circuit node, this excess charge can be collected at the sensitive regions of the circuit node and result in a logic upset-causing voltage spike. The most efficient charge collection regions in microelectronics are strongly reverse-biased pn junction diffusion regions. Logic upsets in CMOS microelectronics are primarily due to excess charge collection at the strongly reverse-biased transistor drain diffusions at each circuit node. Again, considering the CMOS inverter, when VOUT is HIGH the sensitive region is the strongly reverse-biased drain region of the “OFF” NFET. An ion strike in this circumstance to the NFET drain will cause free excess electrons to be collected by the NFET drain region, momentarily driving down the potential at VOUT. This resulting voltage spike can be wrongly interpreted by surrounding circuitry as valid logic data and the incorrect information can be propagated and potentially stored. Similarly, when VOUT is LOW the sensitive region is the strongly reverse-biased drain region of the “OFF” PFET. Now, an ion strike in this circumstance to the PFET drain will cause free excess holes to be collected by the PFET drain region, momentarily driving up the potential at VOUT. This resulting voltage spike can be wrongly interpreted by surrounding circuitry as valid logic data and the incorrect information can be propagated and potentially stored. Similarly in the event of a prompt dose pulse of ionizing radiation the resulting clouds of excess charge generated throughout the semiconductor volume is most effectively collected by strongly reverse-biased regions of the circuit. As microelectronics technologies are increasingly downscaled to extract more performance and density from circuits, their power supply voltages and signal charge levels are similarly downscaled causing a higher susceptibility of the circuit to single event and prompt dose induced logic upsets.
As described previously, when VOUT is HIGH, an ion strike to the “OFF” NFET drain will result in the collection of the excess electrons generated along the track within the p epitaxial layer. (The associated excess holes along the ion track are injected into the p epi/substrate tied to GND). The excess carriers generated beyond the epi layer within the more heavily doped p+ substrate generally quickly recombine and are not collected at the NFET drain, so in this sense the p+ substrate effectively truncates the effect of the ion track so that only the excess electrons along the track within the epi layer are collected by the NFET drain. This is illustrated in FIG. 3. (Note: The depletion regions associated with reverse-biased pn junction regions are not explicitly shown in these illustrations).
In advanced radiation hardened microelectronics, concerted efforts are made to make the epi layer as thin as possible in order to limit the amount of charge that can be collected by a sensitive region due to a single particle event. However, since the epi layer must be thick enough to accommodate the well and diffusions of the complementary transistor type (i.e., the n-well and PFET in FIG. 3), there are limits on how thin one can make the epi layer.
Again, as described previously, when VOUT is LOW, an ion strike to the “OFF” PFET drain will result in the collection of the excess holes generated along the track within the shallow n well. (The associated excess electrons along the ion track are injected into the n well tied to VDD). The excess carriers generated in the p epi/bulk regions below the well are not collected at the PFET drain, so in this sense the reverse-biased n-well/p-epi junction not only truncates the effect of the ion track but also, due to the electrical field at this reverse-biased well/epi junction, draws some of the excess holes generated in the well away from the drain region of PFET so that only a fraction of the excess holes along the track within the shallow n well is collected by the PFET drain, providing enhanced protection against logic upsets. This is illustrated in FIG. 4.
This enhanced protection offered by the well/epi junction to the devices residing in the shallow well has been validated by the results of radiation testing CMOS hardware that correlate to response models that show that the devices lying outside of the well are the most prone to radiation-induced upsets because of their associated longer ion tracks and larger excess charge collection volumes.
Similarly, when VOUT is LOW, the reverse-biased well/epi junction provides enhanced protection against logic upsets to the “OFF” PFET drain regions in the shallow n well in a high-dose rate, prompt dose radiation (e.g., weapons) environment when the energy absorbed from the radiation is converted into pervasive free excess electron-hole pair clouds throughout the entire semiconductor, as depicted in FIG. 5. (Note: Only the excess electron-hole pairs generated within the epi layer and well region are shown in these illustrations since the electron-hole pairs generated deep within the underlying heavily doped p+ substrate quickly recombine at the cessation of the radiation pulse, so they do not affect the devices built of the top surface of the semiconductor).
Again, in this case, the excess carriers generated in the epi/bulk regions below the well are not collected at the PFET drain, so in this sense the reverse-biased n-well/p-epi junction not only restricts the collection volume for excess holes to the shallow well region around the drain but also, due to the electrical field at this reverse-biased well/epi junction, draws some of the excess holes generated in the well region around the drain away from the drain of PFET so that only a fraction of the excess holes within the shallow well region around the drain is collected by the PFET drain, again providing enhanced protection against logic upsets.
When VOUT is HIGH, the heavily doped p+ substrate restricts the collection volume for prompt dose induced excess electrons by the NFET drain to only the p epi region around the NFET drain since the excess carriers generated within the heavily doped substrate would recombine before diffusing to the drain. The absence of a nearby competing charge collecting reverse-biased pn junction like that offered by the well/epi junction for the PFET drains prevents enhanced protection against prompt dose upsets for NFET devices outside of the shallow well. This is illustrated in FIG. 6.
Radiation induced logic upsets and upset causing phenomena (e.g., single-event upsets, single-event transients, single-event functional interrupts, prompt dose upsets, and prompt dose transients) are becoming a much larger problem as technologies are downscaled. Currently practiced design and process hardening techniques alone are inadequate for preventing upsets in scaled technologies. New approaches are needed. The preceding discussion has shown that by virtue of the existence of a reverse-biased well/epi pn junction a CMOS circuit is far less susceptible to the impact of logic upset causing radiation-induced phenomena at the sensitive regions within the shallow well compared to the sensitive regions that lie outside of the shallow well. The reverse-biased well/epi pn junction provides an enhanced level of protection to the devices built within the shallow well. By extension, an improved level of CMOS radiation hardness can be achieved from a novel approach that uses buried power grids. Buried power grids, as will be shown in the next section, extend this concept of enhanced protection also to the devices built outside of the shallow well, thereby improving the overall radiation hardness of CMOS circuits.